In silicon photonics the package costs more than the chip
Coupling light into a waveguide demands sub-micrometre alignment held for the product's life. That is where the money and the yield go.
A silicon photonic die can be fabricated in a CMOS foundry at wafer scale, which makes the chip itself relatively inexpensive at volume. Getting light in and out of it is a different manufacturing problem, and it commonly dominates the finished device cost.
Why coupling is hard
A single-mode optical fibre has a mode field diameter of about ten micrometres. A silicon waveguide is submicron. Coupling between them requires mode conversion, and the alignment tolerance for acceptable loss is a fraction of a micrometre.
That alignment must be achieved during assembly, fixed permanently, and survive thermal cycling, vibration and years of service without drifting.
The approaches
Edge coupling with a spot-size converter — an inverse taper that expands the mode toward the chip edge. Efficient and broadband, but it needs a polished facet and alignment in all axes.
Grating couplers diffract light vertically out of the chip plane, allowing coupling from above. Alignment is more forgiving laterally and the chip needs no facet polish, which suits wafer-level test. The costs are wavelength dependence and polarisation sensitivity.
Photonic wire bonding writes a polymer waveguide between chip and fibre using two-photon polymerisation, adapting to the actual as-placed positions. It removes the alignment tolerance problem by building the connection to fit, at the cost of a slow writing step.
The active alignment cost
Passive alignment — placing components on fiducials and trusting the accuracy — is fast and often not accurate enough. Active alignment turns on the light, measures transmitted power, and adjusts until it peaks.
Active alignment is inherently sequential and slow, and it is the throughput bottleneck in photonic assembly. Each device consumes machine time proportional to the number of optical ports.
Why it matters strategically
The economics of silicon photonics rest on CMOS scale, and packaging does not scale the same way. A process that is per-device, sequential and alignment-limited sits awkwardly against a chip process that is per-wafer and parallel.
Most of the field's manufacturing research is therefore aimed at packaging rather than at the photonics: wafer-level optical test, self-aligning structures, and assembly that tolerates placement error. Whether silicon photonics reaches the cost points its proponents describe depends more on that work than on anything happening in the waveguide.
This article was produced by the LasersNews AI desk and reviewed by our editors.
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